The present invention relates to a semiconductor integrated circuit device and more particularly to a technique which may be effectively adapted to a large scale integrated circuit device comprising RAM macros for high speed operations.
An example of the large scale integrated circuit installing the RAM macros is described in the Japanese Unexamined Patent Application Publication No. Hei 7(1995)-78874 (corresponding U.S. Pat. Nos. 5,898,636 and 6,034,912). This publication proposes a technique to enable high speed and highly efficient circuit design and layout design by replacing a gate array, RAM macro or logic macro in unit of the area to which the clock is supplied from a clock distribution circuit of the final stage for inputting a clock signal from the center area of a semiconductor chip and distribution of clock in the equal distance. An example of a semiconductor integrated circuit device simultaneously loading the DRAM macro and logic core is described in the Japanese Unexamined Patent Application Publication No. Hei 10(1998)-189889 (corresponding U.S. Pat. No. 5, 790,839). This application publication proposes a structure that the synchronous DRAM (hereinafter referred to as SDRAM) is disposed in the upper and lower areas of a semiconductor chip, a logic core is then disposed between the upper and lower SDRAMs of the chip center area, a PLL is then located in the single side of the chip center area and a clock generated therefrom is guided to the center area of the chip to drive each SDRAM macro and logic core after the buffering.
In response to the requirement for high integration density and high speed operation of the elements provided within an LSI in recent years, high speed operation is also required even for the RAM macros loaded in an LSI. In the prior art device explained above, any particular consideration is never taken for high speed operation within the RAM macro itself and data is inputted or outputted from the end terminals thereof. As explained above, with high density integration of elements, it is also possible that a RAM macro has a comparatively large storage capacity. Therefore, when data is inputted to or outputted from the end terminals of the RAM macro, the operation rate is controlled and thereby the high speed operation is prevented due to an access time to a memory cell disposed in the furthest position. Accordingly, the inventors of the present invention propose a semiconductor integrated circuit device provided with a RAM macro which classifies the signals for accessing the RAM macros depending on circuit operation and function and shares such access signals in the optimum manner to assure high speed operation.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device which has realized high speed operation of RAM macro and high integration density. The aforementioned and the other objects and novel characteristics of the present invention will become apparent from description of the present specification and the accompanying drawings thereof.
Typical inventions disclosed in this specification will be explained below briefly. A memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit is disposed to receive a signal required for optimization of signal delay at the center of such four memory arrays, a second input circuit to receive a data input and a control signal thereof is disposed at the center of the Y coordinate corresponding to the extending direction of the word line, an input/output circuit corresponding to a signal other than the signal including a data output is disposed to the end part of the Y coordinate corresponding to the extending direction of data line and an upper layer wiring is used for the wiring forming a memory array as the signal wire to transfer an input signal to the first and second input circuits from an external side of the RAM macro.